Yiqing Zhang

Yiqing Zhang is a highly skilled Staff ASIC Design Engineer at Quantenna Communications, where she has been making significant contributions since June 2019. With a robust background in the semiconductor industry, Yiqing has leveraged her expertise to excel in ASIC design, utilizing her skills in Verilog, RTL implementation, Lint, CDC, and timing analysis. Her journey began at Supermicro, where she honed her skills in PCB verification and testing before transitioning to a role as an ASIC engineer at NXP Semiconductors. With over seven years of experience in the computer hardware and semiconductor sectors, Yiqing’s career showcases her dedication and technical prowess.

Yiqing's academic foundation is as impressive as her professional achievements. She earned her Bachelor of Engineering in Electronic and Electrical Engineering from University College London (UCL), UK, and furthered her education with a Master’s degree in Electrical Engineering, focusing on VLSI design, from the University of Southern California (USC). Her rigorous coursework and research experiences at USC, including VLSI System Design and Digital System Testing, provided her with a solid theoretical and practical understanding of semiconductor technology.

Outside of her professional and academic endeavors, Yiqing is passionate about connecting with others and sharing her experiences. She enjoys engaging in deep conversations and exchanging ideas with friends and colleagues. Her enthusiasm for learning new perspectives and helping others highlights her commitment to personal and professional growth, making her not only a valuable asset to her field but also a supportive and approachable presence in her community.